1. Field of the Invention
The present invention relates generally to the structure of a semiconductor memory element and, more particularly, to memory cells for DRAMs (dynamic random access memories) and a method of making the same.
2. Description of the Related Art
The storage capacity of DRAMs, one of the highly sophisticated high-density storage elements, has increased at a multiplication of 4 in three years, and it is suspected that the DRAMs would be designed to have a storage capacitor increasing from 4M, 16M, 64M and so on with passage of time. In order to accomplish the fabrication of high-density RAMs, memory cells used in the DRAM as storage elements must have a reduced size. On the other hand, in order to obtain an immunity against soft error which would result from radiations and also to secure signals of sufficient S/N ratio, the charge storage capacitance of each memory cell must be of a value higher than a certain minimum value. Because of this, it is not possible to form a charge storage capacitor on a semiconductor surface in DRAMs having a storage capacity higher than 4M. Instead, it is a recent trend to fabricate a three-dimensional memory cell structure wherein the charge storage capacitor is formed in a hole or a groove defined in a semiconductor substrate or over a MOS transistor formed on a surface of the semiconductor substrate.
The technique in which the charge storage capacitor is formed in the hole or groove defined in the semiconductor substrate, that is, inside a trench, is advantageous in that, because the charge storage capacitance can be increased depending on the depth of the trench, the memory cell can be reduced in size. However, this technique has a disadvantage in that it is not technically easy to form a relatively deep trench with good reproducibility.
On the other hand, a stacked memory cell which has the charge storage capacitor formed over the MOS transistor, is relatively suited for production. However, when as compared with the capacitance of the memory cell utilizing the trench, the stacked memory cell has a limited capacitance and is not suited for use in DRAMs where the latter are desired to have an increased storage capacity of from 16M towards 64M. This is because a reduction in cell size tends to result in an abrupt decrease of the charge storage capacitance because the polycrystalline silicon film forming charge storage electrodes in the stacked memory cell has a relatively small thickness, for example, about 0.3 .mu.m which allows most of the charges to be accumulated on surface areas of the electrodes.